//-----------------------------------------------------------------------------
//  Copyright (c) 2013 by HangZhou HenqgQiao Design Corporation. All rights reserved.
//
//  Project  : 
//  Module   : over sample the input data with 8-phases 311M clock
//  Parent   : 
//  Children : 
//
//  Description: 
//
//  Parameters:
//  Local Parameters:
//
//  Notes       : 
//
//  Multicycle and False Paths

module SOH4_OBSIA_DTRM(
   input                        CLKA,
   input                        WEA,
   input[9:0]                   ADDRA,
   input[7:0]                   DINA,

   input                        CLKB,
   input[9:0]                   ADDRB,
   output[7:0]                  DOUTB
   );


wire[9:0]       address_a;
wire[9:0]       address_b;
wire            clock_a;
wire            clock_b;
wire[8:0]       data_a;
wire[8:0]       data_b;
wire            wren_a;
wire            wren_b;
wire[8:0]       q_a;
wire[8:0]       q_b;

SOH4_ALTR_TDP9K_9_9             INST_RAM9K_9_9(
   .address_a                   ( address_a[9:0] ),
   .address_b                   ( address_b[9:0] ),
   .clock_a                     ( clock_a ),
   .clock_b                     ( clock_b ),
   .data_a                      ( data_a[8:0] ),
   .data_b                      ( data_b[8:0] ),
   .wren_a                      ( wren_a ),
   .wren_b                      ( wren_b ),
   .q_a                         ( q_a[8:0] ),
   .q_b                         ( q_b[8:0] )
   );

  assign address_a[9:0]    = ADDRA[9:0];
  assign address_b[9:0]    = ADDRB[9:0];
  assign clock_a           = CLKA;
  assign clock_b           = CLKB;
  assign data_a[8:0]       = {1'b0, DINA[7:0]};
  assign data_b[8:0]       = 9'd0;
  assign wren_a            = WEA;
  assign wren_b            = 1'b0;
  assign DOUTB[7:0]        = q_b[7:0];


endmodule


